In the fabrication of semiconductor integrated circuit (IC) chips, it is frequently necessary to electrically isolate devices that are formed on the surface of the chip. There are various ways of doing this. A way is by using the well-known LOCOS (Local Oxidation Of Silicon) process, wherein the surface of the chip is masked with a relatively hard material such as silicon nitride and a thick oxide layer is grown thermally in an opening in the mask. Another way is to etch a trench in the silicon and then fill the trench with a dielectric material such as silicon oxide.
It is desirable to form these isolation structures early in the process because they can also act as barriers or stops to the lateral diffusion of dopants, thereby allowing a more closely packed device population on the surface of the chip. In short, a dielectric-filled trench can function as a diffusion stop as well as an electrical isolation structure.
The problem with forming a dielectric-filled trench early in the process is that subsequent process steps, which frequently include etching and cleaning, can etch or erode the dielectric material in the trench. This can impair the value of the trench as an isolation structure and can create depressions in the top surface of the chip, rendering further processing more difficult.
This problem is illustrated in FIGS. 1A-1C. In FIG. 1A, a trench 101 has been etched in a semiconductor substrate 100. In FIG. 1B, trench 101 has been filled with a dielectric material 102 and the top surface has been planarized (e.g., by chemical-mechanical polishing) to form an isolation structure. FIG. 1C shows the isolation structure after further processing, with part of the dielectric material 102 removed or eroded so as to form a recess or gap 103 on the top surface of the structure. Dielectric materials that are resistant to etching in normal semiconductor processes (e.g., silicon nitride) tend to be hard, brittle, high-stress materials. When these materials are deposited in a trench they tend to crack.
A second problem stems from the fact that chips are generally divided into two general areas: broad or wide “field” areas and more densely-packed device areas, sometimes referred to as “active” areas. It is preferable to form relatively narrow, deep trenches in the active areas to maintain a tight packing density and to form relatively wide trenches in the field areas to space out the devices over larger distances. This creates a problem in filling the trenches. The narrow trenches may be filled while the wide trenches are difficult to fill. Alternatively, using numerous narrow trenches to cover large distances in the field areas can complicate the topography of the chip.
Accordingly, it would be desirable to develop a flexible, adaptable technique of forming dielectric-filled isolation structures that avoids the erosion of the dielectric fill material during subsequent processing. It would also be desirable to provide for the formation of relatively wide and narrow structures in the field and active regions, respectively, of the chip.